1. Field of the Invention
The present invention relates to a non-volatile memory device, and more particularly, to a non-volatile memory device and programming, reading, and erasing methods thereof.
A claim of priority is made to Korean Patent Application No. 10-2006-0106716, filed Oct. 31, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
F-N tunneling is utilized to program and erase cell transistors contained in non-volatile memory devices, such as NAND type flash memory devices.
For example, F-N tunneling is induced in an erase operation by applying a low voltage (e.g., 0V or ground) to a control gate of a cell transistor, and by applying a high voltage (e.g., 20V) which exceeds a supply voltage to a semiconductor substrate (or bulk) containing the cell transistor. The resultant large voltage differential causes a strong electric field to be formed between the floating gate and the bulk, and F-N tunneling occurs in which electrons are discharged from the floating gate to the bulk. This causes the threshold voltage (Vth) of the erased cell transistor to shift in a negative direction (e.g., Vth≦−3V). In conventional terms, the erased state is designated as data “1”, and a cell transistor in this state is referred to as an “ON” cell.
In a program operation, for example, a high voltage (e.g., 18V) which exceeds a supply voltage is applied to the control gate of the cell transistor, and a low voltage (e.g., 0V or ground) is applied to the drain of the cell transistor and to the semiconductor bulk. When the cell transistor is biased in this manner, F-N tunneling results and electrons are injected to a floating gate of the cell transistor. This causes the threshold voltage (Vth) of the programmed cell transistor to shift in a positive direction (e.g., Vth≧+1V). The programmed state is conventionally designated as data “0”, and the cell transistor is referred to as an “OFF” cell.
FIG. 1 is a block diagram of a conventional NAND type flash memory device 100. The NAND type flash memory device 100 includes a memory cell array 110, a row selecting circuit 130, a row decoder circuit (not shown), a page buffer circuit 150 (or a data sensing and latching circuit), and a column decoder circuit 170.
The memory cell array 110 includes a plurality of memory blocks BLK0 through BLKn each having a plurality of cell strings (n is a positive integer). As illustrated in FIG. 1, each of the cell strings includes of a string selection transistor SST connected to a corresponding bit line, e.g., a bit line BL0, a ground selection transistor GST connected to a common source line CSL, and memory cell transistors MC15 through MC0 connected between the string selection transistor SST and the ground selection transistor GST. Each of the memory cell transistors MC15 through MC0 forms a memory cell. FIG. 1 illustrates the example of 16 memory cells per cell string, but the number of memory cells contained in each string may vary among different NAND flash memory devices.
As shown in FIG. 1, the string selection transistor SST, the memory cells MC15 through MC0, and the ground selection transistor GST are respectively gated to a string selection line SSL, word lines WL15 through WL0, and a ground selection line GSL. Further, as shown, block selection transistors BS17 through BS0 are respectively connected between the lines SSL, WL15 through WL0, and GSL, and lines SS, Si15 through Si0, and GS. The block selection transistors BS17 through BS0 are commonly controlled by a block selection signal BS.
The row selecting circuit 130 is responsive to the row decoder (not shown) to select a word line (or a page) from among the word lines WL0 through WL15 via block selection transistors BS0 through BS17. In a programming mode, the page buffer circuit 150 temporarily stores data to be stored in memory cells of the selected word line (or page). In a read mode, the page buffer circuit 150 senses data stored in the memory cells of the selected word line (or page). The page buffer circuit 150 includes a plurality of page buffers (or data sensing and latching blocks) which respectively correspond to rows (bit lines) related to the selected page. Data bits that are sensed (read) from the memory cells of the selected page are output via the column decoder circuit 170 in predetermined units, e.g., in units of bytes X8.
FIG. 2 is a circuit diagram of another flash memory device 200. This device is at least partially characterized in that wirings for providing voltages to the string selection lines SSL are metal-strapped to one another, as are the wirings for providing voltages to the ground selection lines GSL.
In a standby state prior to the read operation, both the string selection lines SSL and the ground selection lines GSL are discharged to ground voltage. When the read operation is performed, a supply voltage (e.g., VPP) is applied as a block selection signal to the selection transistors of a selected block, while a ground voltage (e.g., 0V) is applied as a block selection signal to the selection transistors of a non-selected block
During the read operation, the voltages of the string selection line SSL and the ground selection line GSL of the selected block are increased from the ground voltage (0 V) to a read voltage VREAD. Further, a ground voltage (0V) is applied to a selected word line WLm of the selected block, and the read voltage is VREAD is applied to the unselected word lines WL0˜WLm−1 and WLm+1˜WLn. In this state, data is read out from the cell transistor(s) of a selected bit line(s).